Generally, the 12.times.12 STS-1 switch, as illustrated in FIG. 1. includes a data memory part 10 storing the inputted STS-1 data, a 90-coding counter 11 generating the write address of the data memory part 10 and the read address of a switch information memory part 12 by performing the count in accordance with the inputted frame pulse, the switch information memory part 12 where the switch information is stored, and data selection part 13 selecting and outputting the data outputted from the data memory part 10.
More specifically, the 90-coding counter 11 generates the write address of the inputted data by counting the inputted frame pulse from 1 to 90, inputs the generated write address into the data memory part 10, and generates and inputs the read address for the reading of the stored switch information data into the switch information memory part 12. The data memory part 10 records the inputted STS-1 data (1-N) according to the above input write address sequentially. That is, the first row of the input data is recorded in address 1 and the second row is recorded in address 2.
The STS-1 data input is made up of 90 rows.times.9 columns and the capacity of data memory part 10 becomes 90 bytes.
In addition, the data memory part 10 is comprised of 1 writing terminal (WADDR) and 11 reading terminal (RADA) s.about.o that the switching between channels is enabled. Therefore, in case of the 12.times.12 STS-1 switch which has twelve RADAS, the read address is inputted from the respective switch information memory part 12.
On the other hand, in case of the 12.times.12 STS-1 switch, the above switch information memory part 12 has 90 units for each STS-1 channel, making 11 bits one unit, and for each unit, 11.about.8 bits represent the STS-1 channel information and 7.about.0.1 bits represent the row information.
Among the switch information output from the above switch information memory part 12, 1.about.7 bits are inputted into the read address of the above data memory part 10 and 8.about.11 bits are inputted into the control signal of the data selection part 13.
Accordingly, the data selection part 12 receiving the control signal of 8.about.11 bits outputted from the above switch information memory part 12 selects and outputs one of N data outputted from the data memory part 10.
Since N.sup.2 data outputted from the data memory part 10 must be connected to the N2 inputs of the n:1 data selection part 15, it is very difficult to manufacture the memory with several RADAs practically.
The attached FIG. 2 shows the configuration of a 12.times.12 STS-1 switch to solve the above problems by equipping the N-coding counter 14 and the N:1 data selector 15 additionally.
The N-coding counter 14 has an operation speed of N times the 90-coding counter 11, and 90-coding counter 11 counts in accordance with the carrying out of the N-coding counter 14.
Besides, the N:1 data selector 15 is used to select one of the switch informations of the address assigned by the above 90coding counter 11 and controlled by the value of the above Ncoding counter 14.
By doing this, the PADAs of the data memory part 10 can be reduced from N to 1.
However, the conventional 12.times.12 STS-1 switch, is very difficult to use practically because the operation frequency is N times the data frequency.